r03ds0047ej0100 rev.1.00 page 1 of 8 jul 21, 2011 preliminary datasheet R2A20112ASP critical conduction mode interleaved pfc control ic description the r2a20112a controls a boost converter to provide an active power factor correction. the r2a20112a adopts critical conduction mode for power factor correction and realizes high ef ficiency and a low switching noise by zero current switching. interleaving function improves ripple current on input or output capacitor by 180 degrees phase shift. soft-star, the feedback loop short detection, two mode over-voltage-protection, over-current-protection, over current on/off timer protection for boost diode short and slave zcd open detection are built in the r2a20112a, and can constitute a power supply system of high reliability with few external parts. features ? absolute maximum ratings ? supply voltage vcc: 24 v ? operating junction temperature tjopr: ?40 to +150c ? electrical characteristics ? vref output voltage vref: 5.0 v ? 1.5% ? uvlo operation start voltage vuvlh: 10.5 v ? 0.7 v ? uvlo operation shutdown voltage vuvll: 9.3 v ? 0.5 v ? uvlo hysteresis voltage hysuvl: 1.2 v ? 0.5 v ? functions ? boost converter control with critical conduction mode ? interleaving control ? soft start function for the reference voltage of error amp ? two mode pfc output over-voltage-protection mode1: dynamic ovp corresponding to a voltage rise by dynamic load change. mode2: static ovp corresponding to over-voltage in stable. ? pfc output dynamic-under-voltage-protection (duvp) ? feedback loop open/short detection ? master and slave independen ce over-current-protection ? 280 ? s restart timer ? slave zcd signal open detection ? over current on/off timer protection for boost diode short ? package ? pb-free sop-16 ordering information part no. package name package code package abbreviation taping abbreviation (quantity) R2A20112ASPw0 fp-16dav prsp0016dh-b sp w (2,000 pcs/reel) r03ds0047ej0100 rev.1.00 jul 21, 2011
R2A20112ASP preliminary r03ds0047ej0100 rev.1.00 page 2 of 8 jul 21, 2011 pin arrangement vcc pgnd gd-s (top view) 1 8 7 6 5 4 3 2 16 9 10 11 12 13 14 15 fb ocp-m zcd-s zcd-m sgnd comp tm ramp rt vref gd-m ocp-s ss pin functions pin no. pin name function 1 zcd-m master converter zero current detection input terminal 2 zcd-s slave converter zero current detection input terminal 3 tm over current on/off timer protection terminal 4 vref reference voltage output terminal 5 sgnd signal ground 6 ramp ramp waveform setting terminal 7 rt oscillator frequency setting terminal 8 comp error amplifier output terminal 9 fb error amplifier input terminal 10 ss soft start time setting terminal 11 ocp-s slave converter overcurrent detection terminal 12 ocp-m master converter overcurrent detection terminal 13 gd-s slave converter power mosfet drive terminal 14 pgnd power ground 15 gd-m master converter power mosfet drive terminal 16 vcc supply voltage terminal
R2A20112ASP preliminary r03ds0047ej0100 rev.1.00 page 3 of 8 jul 21, 2011 block diagram ocp comp1 vfb=2.49v ovp block fb gd disable comp discharge on: 10.5v off: 9.3v vzcd_lo=1.3v 300mvhys -0.1v ~ 4.5v 4.3v vref error amp m-ocp 0.3v s-ocp vref 10 a10 a 50a zcd comp1 zcd comp2 sw comp 5a 5a vref iramp tstart dynamic uvp vfb 0.93v ramp level shift 0.9v (design spec) uvlo vref: 5v vref: 5v vcc vtm=3.6v 2.2vhys 40a 10a vref hi: on 5a stop gd logic + ? ocp comp2 clamp -0.1v ~ 4.5v + ? ? + clamp vcc zcd-m zcd-s tm vref sgnd rt ramp comp gd-m gd-s ocp-m ocp-s fb ss pgnd iramp vref uvl fblow + ? + ? + ? ? + ? +
R2A20112ASP preliminary r03ds0047ej0100 rev.1.00 page 4 of 8 jul 21, 2011 absolute maximum ratings (ta = 25c) item symbol ratings unit notes supply voltage vcc ?0.3 to +24 v gd terminal peak current ipk-gd ?300 +1200 ma 3 gd terminal dc current idc-gd ?15 +60 ma zcd terminal current izcd +3 ?3 ma rt terminal current irt ?200 ? a 4 vref terminal current iref ?5 ma cref min 1000 pf vref terminal load capacitor cref max 1 ? f comp terminal current icomp ? 1 ma vt-group1 ?0.3 to vcc v 5 terminal voltage vt-group2 ?0.3 to vref v 6 vref terminal voltage vt-ref ?0.3 to vref + 0.3 v ocp terminal voltage vt-ocp *?1 to vref v 7 power dissipation pt 1 w 8 operating junction temperatur e tj-opr ?40 to +150 c storage temperature tstg ?55 to +150 c notes: 1. rated voltages are with reference to the pgnd terminal. 2. for rated currents, inflow to the ic is indicated by (+), and outflow by (?). 3. shows the transient current when driving a capacitive load. 4. rt terminal's resistor is fixed 33 k ? to gnd. 5. this is the rated voltage for the following pins: nothing 6. this is the rated voltage for the following pins: fb, ss, ramp, tm 7. minus value is peak voltage. do not impress the dc voltage of the minus. 8. ? ja = 120c/w this value is a thing mounting on 40 ? 40 (thickness: 1.6 mm) [mm 2 ], a glass epoxy board of wiring density 10%.
R2A20112ASP preliminary r03ds0047ej0100 rev.1.00 page 5 of 8 jul 21, 2011 electrical characteristics (ta = 25c, vcc = 12 v, rt = 33 k ? , ramp = 820 pf, tm = 2.2 ? f, ss = 1.0 ? f, ocp = gnd) item symbol min typ max unit test conditions uvlo turn-on threshold vuvlh 9.8 10.5 11.2 v uvlo turn-off threshold vuvll 8.8 9.3 9.8 v uvlo hysteresis hysuvl 0.7 1.2 1.7 v standby current istby ? 85 170 ? a vcc = 8.9 v supply operating current icc ? 4.2 6.3 ma output voltage vref 4.925 5.00 5.075 v isource = ?1 ma line regulation vref-line ? 5 20 mv isource = ?1 ma vcc = 10 v to 24 v load regulation vref-load ? 5 20 mv isource = ?1 ma to ?5 ma vref temperature stability dvref ? ? 80 ? ppm/c ta = ?40 to +125c * 1 feedback voltage vfb 2.452 2.490 2.528 v fb-comp short input bias current ifb ?0.5 ?0.3 ?0.1 ? a measured pin: fb fb = 3 v * 1 open loop gain av ? 60 ? db * 1 upper clamp voltage vclamp-comp 4.2 4.3 4.4 v fb = 2.0 v low voltage vl-comp ? 0.1 0.3 v fb = 3.0 v source current isrc-comp ? ?120 ? ? a fb = 1.5 v comp = 2.5 v * 1 sink current isnk-comp ? 330 ? ? a fb = 3.5 v comp = 2.5 v error amplifier transconductance gm 120 200 290 ? s fb = 2.45v ? 2.55 v comp = 2.5 v ramp charge current at duvp disable condition ic-ramp1 ?60 ?50 ?40 ? a fb = 2.4 v ramp charge current at duvp enable condition ic-ramp2 ?32 ?25 ?18 ? a fb = 2 v ramp discharge current id-ramp 7 15 29 ma ramp = 1 v ramp low voltage vl-ramp ? 17 200 mv isink = 100 ? a phase delay phase 160 180 200 deg slave control on time ratio ton-ratio 0 ? 5 % fb = 2.5 v, comp = 2 v * 1, 2 notes: * 1 design spec * 2 ton-ratio = ton-s ton-m 100 [%] 1 ? phase = tdelay tperiod 360 [deg] gd-m gd-s tperiod (100s) tdelay ton-m (50s) ton-s
R2A20112ASP preliminary r03ds0047ej0100 rev.1.00 page 6 of 8 jul 21, 2011 electrical characteristics (cont.) (ta = 25c, vcc = 12 v, rt = 33 k ? , ramp = 820 pf, tm = 2.2 ? f, ss = 1.0 ? f, ocp = gnd) item symbol min typ max unit test conditions gate drive rise time tr-gd ? 20 100 ns fb-comp short cl = 100 pf tr 90% 10% gate drive fall time tf-gd ? 5 30 ns fb-comp short cl = 100 pf tf 90% 10% vol1-gd ? 0.02 0.1 v isink = 2 ma gate drive low voltage vol2-gd ? 0.01 0.2 v isink = 1 ma, vcc = 5 v gate drive (gd-m & gd-s) gate drive high voltage voh-gd 11.5 11.9 ? v isource = ?2 ma * 1 ocp threshold voltage vocp 0.27 0.30 0.33 v over current protection (ocp-m & ocp-s ocp source current iocp ?10 ?5 ?2.5 ? a ocp = 0 v on/off timer threshold voltage vtm 3.52 3.6 3.68 v on/off timer hysteresis hys-tm 2.1 2.2 2.3 v charge current isrc-tm ?54 ?45 ?36 ? a tm = 2 v, ocp-m = 1 v discharge current at tm disable condition isnk-tm1 36 45 54 ? a tm = 2 v on/off timer protection for boost diode short discharge current at tm enable condition isnk-tm2 4.2 5 5.8 ? a tm = 5 v to 2 v dynamic ovp threshold voltage vdovp vfb ? 1.035 vfb ? 1.050 vfb ? 1.065 v comp = 2.5 v static ovp threshold voltage vsovp vfb ? 1.075 vfb ? 1.090 vfb ? 1.105 v comp = 2.5 v static ovp hysteresis hys-sovp 50 100 150 mv comp = 2.5 v dynamic uvp threshold voltage vduvp ? vfb ? 0.930 vfb ? 0.950 v comp = 2.5 v * 1 fb low detect threshold voltage vfblow 0.45 0.50 0.55 v comp = 2.5 v pfc output abnormality protection fb low detect hysteresis hysfblow 0.16 0.20 0.24 v comp = 2.5 v upper clamp voltage vzcdh 4.0 4.5 5.0 v isource = ?3 ma lower clamp voltage vzcdl ?0.5 ?0.1 0.4 v isink = 3 ma zcd low threshold voltage vzcd-lo 0.9 1.3 1.6 v * 1 zcd hysteresis hyszcd 130 300 410 mv * 1 zero current detector (zcd-m & zcd-s) input bias current izcd ?14 ?10 ?6 ? a 1.2 v < vzcd < 2.5 v zcd-s open detector slave zcd open detect delay time tzcds ? 100 ? ms zcd-s: open gate drive 10 khz * 1 soft start charge current ic-ss ?14 ?10 ?6 ? a ss = 3 v, fb = 1 v restart restart time delay tstart 210 280 350 ? s zcd-m = 10 k ? to gnd zcd-s = 10 k ? to gnd * 2 notes: * 1 design spec * 2 tstart (280s) [ a period without zcd-m trigger] restart pulse width: 1s (design spec) zcd-m vzcd-lo (1.3v: provide 300mv hysteresis) gd-m
R2A20112ASP preliminary r03ds0047ej0100 rev.1.00 page 7 of 8 jul 21, 2011 system diagram from gd-m to q1 gate q1 3m pfc out (390vdc, 400w) gnd vrb1 t1 0.1 from gd-s q2 t2 to q2 gate 33k d2 0.02 1000p 200 1.0 R2A20112ASP vcc gd-m zcd-m zcd-s tm vref sgnd ramp comp gd-s ocp-m ocp-s fb ss pgnd 1 1000p 200 0.1 220 2.2 1 470p d1 820k 51k aux rt 220 33k 33k 0.02 + 470 (450v) 2
R2A20112ASP preliminary r03ds0047ej0100 rev.1.00 page 8 of 8 jul 21, 2011 package dimensions note) 1. dimensions"*1 (nom)"and" *2" do not include mold flash. 2. dimension"*3"does not include trim offset. 10.06 1.15 0.12 0 8 7.80 0.15 0.20 0.25 0.46 0.00 0.10 0.20 5.50 0.50 0.70 0.90 2.20 reference symbol dimension in millimeters min nom max 10.5 e h e l a d e a 2 a 1 b p b 1 c x y z l 1 c 1 0.34 0.40 8.00 7.50 1.27 0.15 0.80 previous code jeita package code renesas code prsp0016dh-b fp-16dav mass[typ.] 0.24g p-sop16-5.5x10.06-1.27 terminal cross section ( ni/pd/au plating ) c detail f l y s s index mark f *3 mx 9 16 18 *2 *1 a e z e d l 1 a 1 b p b p h e
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